Open to VLSI / Semiconductor internships — Summer 2026

Hi, I'm Yelleti Harshavardhan

Second Year B.Tech — Electronics & Communication Engineering @ KLEF · CGPA 9.68 / 10. Building VLSI Engineer projects in Verilog, FPGA and ASIC flows — preparing for a career in the semiconductor industry.

Narsipatnam, Andhra Pradesh, India KLEF · ECE
SYSTEM: ONLINEDEV: RV32I_CORE
Yelleti Harshavardhan
Y. Harshavardhan
RTL & FPGA Developer
$ domainVLSI & RTL Design
$ targetFPGA & ASIC Flows
$ toolchainVivado · ModelSim · DC
$ researchGDI Logic & Device Phys.
$ educationCGPA 9.68 / 10 · 3rd Year
9.68
Current CGPA
0+
Projects & Repos
0+
Certifications
0
Coding Platforms
0+
Research Drafts
About

Engineering future silicon, one RTL block at a time.

I'm a motivated second-year B.Tech ECE student at Koneru Lakshmaiah Education Foundation (KLEF University) with a CGPA of 9.68 / 10, preparing for a career in VLSI and Semiconductor Engineering.

My core interests are Digital VLSI Design, RTL Design in Verilog HDL, FPGA Design, Digital and Analog Electronics, CMOS fundamentals, MOSFET analysis, and Computer Organization & Architecture. I'm also actively learning Embedded Systems.

Alongside hardware, I work with Python and Machine Learning fundamentals, use Git & GitHub for every project, and keep sharpening my problem-solving on competitive-programming platforms.

Digital VLSI DesignRTL Design (Verilog HDL)FPGA DesignDigital ElectronicsAnalog ElectronicsCMOS FundamentalsMOSFET AnalysisComputer Organization & ArchitectureEmbedded Systems (Learning)PythonMachine Learning FundamentalsGit & GitHubProblem Solving
Education
B.Tech ECE · KLEF
CGPA
9.68 / 10
Based in
Narsipatnam, India
Seeking
VLSI / RTL Intern
Education

Academic Excellence & ECE Coursework

Strong theoretical foundation coupled with practical laboratory verification.

ECE 3102

Digital VLSI Design

ECE 3105

RTL Design with Verilog

ECE 2101

Digital Electronics

ECE 2202

Analog Electronics

ECE 3201

Computer Organization & Architecture

ECE 2103

Signals & Systems

ECE 3204

Embedded Systems

ECE 3104

Microprocessors & Microcontrollers

Skills

A stack built for silicon.

VLSI & Semiconductor

Digital VLSI DesignProficient
RTL Design (Verilog HDL)Familiar
FPGA DesignFamiliar
CMOS FundamentalsFamiliar
MOSFET AnalysisProficient

Electronics

Digital ElectronicsProficient
Analog ElectronicsProficient

Computer Organization & Architecture

Computer OrganizationProficient
Computer ArchitectureProficient

Embedded Systems

Embedded Systems (Learning)Familiar

Programming

CProficient
PythonProficient
Verilog HDLFamiliar
Problem SolvingProficient

Machine Learning

Machine Learning FundamentalsFamiliar
NumPy / PandasFamiliar

EDA & Simulation Tools

Xilinx VivadoFamiliar
ModelSimFamiliar
NI MultisimFamiliar
LTspiceFamiliar
Cisco Packet TracerProficient
Git & GitHubProficient
Projects

Shipping hardware ideas.

Selected RTL, FPGA, embedded and ML projects.

RTL · Computer Architecture

Pipelined RISC-V (RV32I) Processor Core

Designed and verified a 5-stage pipelined RISC-V (RV32I) processor core in Verilog HDL, featuring hazard detection, forwarding units, and instruction/data cache simulation.

  • 5-stage pipelined execution path
  • Hazard detection & forwarding logic
  • Instruction & Data cache integration
Verilog HDLXilinx VivadoModelSimGTKWave
View on GitHub
RTL · DSP Architecture

FPGA-Based 8-Point Fast Fourier Transform (FFT) Processor

Implemented a butterfly-architecture-based 8-point FFT processor in Verilog for high-speed digital signal processing on FPGA, verifying accuracy against MATLAB models.

  • Butterfly computing unit optimization
  • Fixed-point arithmetic scaling
  • Validation with MATLAB test signals
Verilog HDLXilinx VivadoMATLAB
View on GitHub
RTL · FPGA

FPGA-Based 8-Bit ALU Using Verilog HDL

Designed and verified an 8-bit Arithmetic Logic Unit in Verilog HDL targeting an FPGA, with testbench-driven simulation and synthesis.

  • 8-bit ALU operations
  • Testbench verification
  • FPGA synthesis flow
Verilog HDLXilinx VivadoFPGA
View on GitHub
Analog VLSI

DC Analysis and Short Channel Effects in MOSFETs

Analyzed NMOS and PMOS transistor characteristics including short-channel effects and channel length modulation across operating regions.

  • I_D-V_GS / I_D-V_DS plots
  • Short-channel analysis
  • Device-level insight
NI MultisimLTspice
View on GitHub
Python Full Stack

Student Activity & Achievement Management System

Web-based system to manage student extracurricular activities and achievements, built with full-stack Python.

  • CRUD workflows
  • Activity tracking
  • Data management
PythonFull StackWeb
View on GitHub
Python · ML

Machine Learning for Weather Data Analysis

End-to-end weather data pipeline using regression and clustering algorithms with standard evaluation metrics.

  • EDA pipeline
  • Regression + K-Means
  • Model evaluation
Pythonscikit-learnPandas
View on GitHub
Experience

Trainings, research & projects.

01 May 2026 – 15 June 2026

Summer Internship — FPGA & VLSI Design

Sense Semiconductor & IT Solutions Pvt. Ltd. (SSIT)
  • Completed the Foundation Course in FPGA & VLSI as part of SSIT's Summer Internship Program 2026 (Cert. No. SSIT-2026-1196).
  • Hands-on training in digital design, RTL workflows and FPGA-based prototyping.
  • Built industry-oriented mini-projects demonstrating problem-solving, debugging and communication skills.
April 2026 – June 2026 (8 weeks)

Virtual Internship — Siemens Conceptual CAE Design & Simulation

AICTE – EduSkills (Supported by Siemens)
  • Selected for the 8-week AICTE–EduSkills Virtual Internship Program in Siemens Conceptual CAE Design & Simulation.
  • Worked through structured weekly modules on Polyaxofluxe Foaming with Inspire, Additive Manufacturing and Structural Analysis certification.
  • Completed weekly assessments, project documentation and a Final Assessment Test to earn the Virtual Internship Certificate.
2024 — Present

Research & Project Work — VLSI / RTL

KLEF University
  • Designed and verified multiple RTL modules in Verilog on FPGA boards.
  • Worked on pipelined processor and DSP datapath projects.
  • Serving as a Reviewer for the International Journal of Innovative Research in Technology (IJIRT, ISSN 2349-6002).
Research

Publications & ongoing research.

Hardware design, FPGA systems and ML for EDA.

2026

Evaluation of Ripple Carry and Carry Look-Ahead Adder-Based 8-Bit ALU Architectures Using Verilog HDL

Conference Paper • 2026

Evaluation of Ripple Carry and Carry Look-Ahead adder-based 8-bit ALU architectures implemented using Verilog HDL for FPGA-based digital design. This is my first research publication, marking the beginning of my work in VLSI research.

VLSIVerilog HDL8-bit ALURipple CarryCarry Look-Ahead
Certifications

Credentials & Certifications

Professional and technical validations from industry leaders.

Sense Semiconductor (SSIT)
FPGA & VLSI Design Internship Certificate
AICTE – EduSkills (Siemens)
Siemens Conceptual CAE Design & Simulation
IJIRT Reviewer Board
Journal Reviewer Appointment Certificate
TARAS
AI & Machine Learning with Python Programming
Linux Foundation
Introduction to Hands-on Linux
Cisco Networking Academy
Getting Started with Cisco Packet Tracer
Coursera
Python for Everybody Specialization
Achievements

Recognition & milestones.

CGPA 9.68 / 10
Top of class, second-year ECE
Smart India Hackathon
Participant
CodeChef 3-Star
Active competitive programmer
ORCID Researcher
Active research profile
Multi-platform Coder
LeetCode · CF · HR · GFG
Open Source Contributor
GitHub @Born-as-Harsha
Contact

Let's build something silicon-grade.

Open to internships, research collaborations and open-source projects.

Reach out — I usually reply within 24 hours.

For internship opportunities, research, or open-source collabs.