Yelleti Harshavardhan

Designed and verified a 5-stage pipelined RISC-V (RV32I) processor core in Verilog HDL, featuring hazard detection, forwarding units, and instruction/data cache simulation.

• 5-stage pipelined execution path
• Hazard detection & forwarding logic
• Instruction & Data cache integration

Implemented a butterfly-architecture-based 8-point FFT processor in Verilog for high-speed digital signal processing on FPGA, verifying accuracy against MATLAB models.

• Butterfly computing unit optimization
• Fixed-point arithmetic scaling
• Validation with MATLAB test signals

Designed and verified an 8-bit Arithmetic Logic Unit in Verilog HDL targeting an FPGA, with testbench-driven simulation and synthesis.

• 8-bit ALU operations
• Testbench verification
• FPGA synthesis flow

Analyzed NMOS and PMOS transistor characteristics including short-channel effects and channel length modulation across operating regions.

• I_D-V_GS / I_D-V_DS plots
• Short-channel analysis
• Device-level insight

Web-based system to manage student extracurricular activities and achievements, built with full-stack Python.

• CRUD workflows
• Activity tracking
• Data management

End-to-end weather data pipeline using regression and clustering algorithms with standard evaluation metrics.

• EDA pipeline
• Regression + K-Means
• Model evaluation

• Completed the Foundation Course in FPGA & VLSI as part of SSIT's Summer Internship Program 2026 (Cert. No. SSIT-2026-1196).
• Hands-on training in digital design, RTL workflows and FPGA-based prototyping.
• Built industry-oriented mini-projects demonstrating problem-solving, debugging and communication skills.

• Selected for the 8-week AICTE–EduSkills Virtual Internship Program in Siemens Conceptual CAE Design & Simulation.
• Worked through structured weekly modules on Polyaxofluxe Foaming with Inspire, Additive Manufacturing and Structural Analysis certification.
• Completed weekly assessments, project documentation and a Final Assessment Test to earn the Virtual Internship Certificate.

• Designed and verified multiple RTL modules in Verilog on FPGA boards.
• Worked on pipelined processor and DSP datapath projects.
• Serving as a Reviewer for the International Journal of Innovative Research in Technology (IJIRT, ISSN 2349-6002).

Evaluation of Ripple Carry and Carry Look-Ahead adder-based 8-bit ALU architectures implemented using Verilog HDL for FPGA-based digital design. This is my first research publication, marking the beginning of my work in VLSI research.